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SEMICONDUCTOR
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
July 1996
0.3A, 60V, ESD Rated, Current Limited, Voltage Clamped Logic Level N-Channel Enhancement-Mode Power MOSFETs
Packages
JEDEC TO-220AB
SOURCE DRAIN GATE
Features
* * * * * * * 0.30A, 60V rDS(ON) = 6.0 Built in Current Limit ILIMIT 0.140 to 0.210A at 150oC Built in Voltage Clamp Temperature Compensating PSPICE Model 2kV ESD Protected Controlled Switching Limits EMI and RFI
DRAIN (FLANGE)
Description
The RLD03N06CLE, RLD03N06CLESM and RLP03N06CLE are intelligent monolithic power circuits which incorporate a lateral bipolar transistor, resistors, zener diodes and a power MOS transistor. The current limiting of these devices allow it to be used safely in circuits where a shorted load condition may be encountered. The drain-source voltage clamping offers precision control of the circuit voltage when switching inductive loads. The "Logic Level" gate allows this device to be fully biased on with only 5.0V from gate to source, thereby facilitating true on-off power control directly from logic level (5V) integrated circuits. The RLD03N06CLE, RLD03N06CLESM and RLP03N06CLE incorporate ESD protection and are designed to withstand 2kV (Human Body Model) of ESD.
PACKAGING AVAILABILITY PART NUMBER RLD03N06CLE RLD03N06CLESM RLP03N06CLE PACKAGE TO-251AA TO-252AA TO-220AB BRAND 03N06C 03N06C 03N06CLE
G DRAIN (FLANGE)
JEDEC TO-251AA
SOURCE DRAIN GATE
JEDEC TO-252AA
DRAIN (FLANGE) GATE SOURCE
Symbol
D
NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in tape and reel, i.e. RLD03N06CLESM9A.
S
Formerly developmental type TA49026.
Absolute Maximum Ratings
TC = +25oC RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE 60 60 +5.5
Drain Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS Drain Gate Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate Source Voltage (Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Reverse Voltage Gate Bias Not Allowed Drain Current RMS Continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Power Dissipation TC = +25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate above +25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PT Electrostatic Discharge Rating MIL-STD-883, Category B(2) . . . . . . . . . . . . . . . . . . . . . . ESD Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSTG, TJ
UNITS V V V
Self Limited 30 0.2 2 -55 to +175 W W/oC KV oC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper ESD Handling Procedures. Copyright
(c) Harris Corporation 1996
File Number
3948.3
1
Specifications RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
Electrical Specifications TC = +25oC, Unless Otherwise Specified
PARAMETERS Drain-Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V VGS = VDS, ID = 250A VDS = 45V, VGS = 0V TJ = +25oC TJ = +150oC TJ = +25oC TJ = +150oC On Resistance rDS(ON) ID = 0.100A, VGS = 5V TJ = +25oC TJ = +150oC TJ = +25oC TJ = +150oC MIN 60 1 280 140 VDS = 25V, VGS = 0V, f = 1MHz TO-220 Package TO-251 and TO-252 Packages TYP 100 65 3.0 MAX 85 2.5 50 200 5 20 6.0 12.0 420 210 7.5 2.5 5.0 7.5 5.0 12.5 5.0 80 100 UNITS V V A A A A mA mA s s s s s s pF pF pF
oC/W oC/W oC/W
Gate-Source Leakage Current
IGSS
VGS = 5V
Limiting Current
IDS(LIMIT)
VDS = 15V, VGS = 5V
Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
tON tD(ON) tR tD(OFF) tF tOFF CISS COSS CRSS RJC RJA
VDD = 30V, ID = 0.10A, RL = 300, VGS = 5V, RGS = 25
Source-Drain Diode Ratings and Specifications
PARAMETERS Forward Voltage Reverse Recovery Time SYMBOL VSD tRR TEST CONDITIONS ISD = 0.1A ISD = 0.1A, dISD/dt = 100A/s MIN TYP MAX 1.5 1.0 UNITS V ms
2
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Typical Performance Curves
1 OPERATION IN THIS AREA IS LIMITED BY JUNCTION TEMPERATURE ZJC , NORMALIZED THERMAL RESPONSE 1 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE PDM TC = +25oC 10
ID , DRAIN CURRENT (A)
DC
25oC 175oC
OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON)
0.1 1 10 VDS , DRAIN-TO-SOURCE VOLTAGE (V) 100
0.01 10-5
t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC + TC 10-2 10-1 100 101
10-4
10-3
t, RECTANGULAR PULSE DURATION (s)
FIGURE 1. SAFE OPERATING AREA CURVE
FIGURE 2. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
2.0 ID , NORMALIZED DRAIN CURRENT POWER DISSIPATION MULTIPLIER -40 0 40 80 120 160 200
1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC)
1.5
1.0
0.5
0 -80
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 3. TYPICAL NORMALIZED DRAIN CURRENT vs JUNCTION TEMPERATURE
PULSE DURATION = 250s, TC = +25oC
FIGURE 4. NORMALIZED POWER DISSIPATION vs TEMPERATURE DERATING CURVE
VDD = 15V -55oC 0.50 PULSE TEST PULSE DURATION = 250s DUTY CYCLE = 0.5% MAX +25oC
0.40
0.60 ID(ON) , ON STATE DRAIN CURRENT (A)
VGS = 5V
VGS = 7.5V VGS = 4V
ID , DRAIN CURRENT (A)
0.30 VGS = 3V 0.20
0.40 0.30
0.20 +175oC 0.10 0 0.0
0.10
0
0
1.0
2.0
3.0
4.0
5.0
1.0
2.0
3.0
4.0
5.0
VDS , DRAIN-TO-SOURCE VOLTAGE (V)
VGS , GATE-TO-SOURCE VOLTAGE (V)
FIGURE 5. TYPICAL SATURATION CHARACTERISTICS
FIGURE 6. TYPICAL TRANSFER CHARACTERISTICS
3
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Typical Performance Curves (Continued)
rDS(ON) , NORMALIZED ON RESISTANCE 2.5 PULSE DURATION = 250s, VGS = 5V, ID = 0.30A VGS(TH) , NORMALIZED GATE THRESHOLD VOLTAGE 2.0 VGS = VDS, ID = 250A
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0.0 -80
-40
0
40
80
120
160
200
0.0 -80
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 7. NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE
FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs TEMPERATURE
TC = +25oC TEMPERATURES LISTED ARE STARTING JUNCTION TEMPERATURES
1.5
I(CLAMP) , CLAMPED DRAIN CURRENT (A)
2.0 BVDSS , NORMALIZED DRAIN-TOSOURCE BREAKDOWN VOLTAGE
ID = 20mA
1
1.0
+25oC +50oC +75oC +100oC +150oC 0.1 0.001 0.01 0.1 tAV , TIME IN CLAMP (s) 1 +125oC 10
0.5
0.0 -80
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE vs TEMPERATURE
300 VGS = 0V, FREQUENCY (f) = 1MHz VDS , DRAIN SOURCE VOLTAGE (V)
FIGURE 10. SELF-CLAMPED INDUCTIVE SWITCHING
60
5.00 VGS , GATE SOURCE VOLTAGE (V)
45 VDD = BVDSS
3.75
C, CAPACITANCE (pF)
200
30 0.75 BVDSS 15 0.50 BVDSS 0.25 BVDSS RL = 600 IG(REF) = 0.1mA VGS = 5V
2.50
CISS 100 COSS
1.25
CRSS 0 0 5 10 15 20 25
0
0.00
VDS , DRAIN-TO-SOURCE VOLTAGE (V)
10 --------------------I G ( AC T )
I G ( REF )
t, TIME (s)
--------------------40 I G ( AC T )
I G ( REF )
FIGURE 11. TYPICAL CAPACITANCE vs DRAIN-TO-SOURCE VOLTAGE
FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT. REFER TO HARRIS APPLICATION NOTES AN7254 AND AN7260
4
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Test Circuit and Waveform
VDD tON tD(ON) tR VDS VDS 90% tOFF tD(OFF) tF 90%
RL
VGS 10% DUT 0V VGS RGS 10% 50% PULSE WIDTH 50% 90% 10%
FIGURE 13. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 14. RESISTIVE SWITCHING WAVEFORMS
Detailed Description
Temperature Dependence of Current Limiting and Switching Speed Performance The RLD03N06CLE, RLD03N06CLESM and RLP03N06CLE are a monolithic power device which incorporates a Logic Level power MOSFET transistor with a current sensing scheme and control circuitry to enable the device to self limit the drain source current flow. The current sensing scheme supplies current to a resistor that is connected across the base to emitter of a bipolar transistor in the control section. The collector of this bipolar transistor is connected to the gate of the power MOSFET transistor. When the ratiometric current from the current sensing reaches the value required to forward bias the base emitter junction of this bipolar transistor, the bipolar "turns on". A resistor is incorporated in series with the gate of the power MOSFET transistor allowing the bipolar transistor to adjust the drive on the gate of the power MOSFET transistor to a voltage which then maintains a constant current in the power MOSFET transistor. Since both the ratiometric current sensing scheme and the base emitter unction voltage of the bipolar transistor vary with temperature, the current at which the device limits is a function of temperature. This dependence is shown in Figure 3. The resistor in series with the gate of the power MOSFET transistor also results in much slower switching performance than in standard power MOSFET transistors. This is an advantage where fast switching can cause EMI or RFI. The switching speed is very predictable. DC Operation The limit on the drain to source voltage for operation in current limiting on a steady state (DC) basis is shown in the equation below. The dissipation in the device is simply the applied drain to source voltage multiplied by the limiting current. This device, like most power MOSFET devices today, is limited to 175oC. The maximum voltage allowable can, therefore, be expressed as shown in Equation 1:
( 150C - TA MBIENT ) V DS = ------------------------------------------------------I LM * ( R +R )
JC JA
Duty Cycle Operation In many applications either the drain to source voltage or the gate drive is not available 100% of the time. The copper header on which the RLD03N06CLE, RLD03N06CLESM and RLP03N06CLE is mounted has a very large thermal storage capability, so for pulse widths of less then 1ms, the temperature of the header can be considered a constant, thereby the junction temperature can be calculated simply as shown in Equation 2:
T C = ( V DS * I D * D * R CA ) + TA MBIENT
(EQ. 2)
Generally the heat storage capability of the silicon chip in a power transistor is ignored for duty cycle calculations. Making this assumption, limiting junction temperature to 175oC and using the TC calculated in Equation 2, the expression for maximum VDS under duty cycle operation is shown in Equation 3:
o 150 C - T C V DS = ----------------------------------------I LM * D * R JC
(EQ. 3)
These values are plotted as Figures 16 through 21 for various heatsink thermal resistances. Limited Time Operations Protection for a limited period of time is sufficient for many applications. As stated above the heat storage in the silicon chip can usually be ignored for computations of over 10 ms, thereby the thermal equivalent circuit reduces to a simple enough circuit to allow easy computation on the limiting conditions. The variation in limiting current with temperature complicates the calculation of junction temperature, but a simple straight line approximation of the variation is accurate enough to allow meaningful computations. The curves shown as Figures 22 through 25 (RLP03N06CLE) and Figure 26 through 29 (RLD03N06CLE and RLD03N06CLESM) give an accurate indication of how long the specified voltage can be applied to the device in the current limiting mode without exceeding the maximum specified 175oC junction temperature. In practice this tells you how long you have to alleviate the condition causing the current limiting to occur.
(EQ. 1)
The results of this equation are plotted in Figure 15 for various heatsinks.
5
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Performance Curves
HEAT SINK THERMAL RESISTANCE = HSTR 90 VDS , DRAIN TO SOURCE VOLTAGE (V) HSTR = 0oC/W HSTR = 1oC/W HSTR = 2oC/W HSTR = 5oC/W 60 HSTR = 10oC/W 45 TJ = 175oC ILIM = 0.210A RJC = 5.0oC/W 90 DC = 50% 75 DC = 5% 60 DC = 10% DC = 20% DC = 2% DUTY CYCLE = DC MAX PULSE WIDTH = 100ms
VDS , APPLIED VOLTAGE (V)
75
45
30
HSTR = 25oC/W HSTR = 80oC/W
30 TJ = 175oC ILIM = 0.210A RJC = 5.0oC/W 125 150 TA , AMBIENT TEMPERATURE (oC) 175
15
15
0
25
50
75 100 125 150 TA , AMBIENT TEMPERATURE (oC)
175
0 100
FIGURE 15. DC OPERATION IN CURRENT LIMITING
FIGURE 16. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HEATSINK THERMAL RESISTANCE = 1oC/W)
DUTY CYCLE = DC MAX PULSE WIDTH = 100ms
90 VDS , DRAIN TO SOURCE VOLTAGE (V)
DUTY CYCLE = DC
MAX PULSE WIDTH = 100ms VDS , DRAIN TO SOURCE VOLTAGE (V) DC = 2%
90
DC = 20% 75 60 DC = 50% 45
75 DC = 50% 60 DC = 20% DC = 5% DC = 10%
DC = 2% DC = 5% DC = 10%
45 30 TJ = 175oC ILIM = 0.210A RJC = 5.0oC/W 125 150 TA , AMBIENT TEMPERATURE (oC) 175
30 TJ = 175oC ILIM = 0.210A RJC = 5.0oC/W 100 125 150 TA , AMBIENT TEMPERATURE (oC) 175
15 0 100
15
0 75
FIGURE 17. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HSTR = 2oC/W)
DUTY CYCLE = DC 90 VDS , DRAIN TO SOURCE VOLTAGE (V) DC = 2% DC = 5% DC = 10% MAX PULSE WIDTH = 100ms
FIGURE 18. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HSTR = 5oC/W)
DUTY CYCLE = DC 90 VDS , DRAIN TO SOURCE VOLTAGE (V) MAX PULSE WIDTH = 100ms
DC = 20% 75 DC = 50% 60
DC = 20% 75
DC = 10%
DC = 2% DC = 5%
60
45
45 DC = 50% TJ = 175oC ILIM = 0.210A RJC = 5.0oC/W 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) 175
30 TJ = 175oC ILIM = 0.210A RJC = 5.0oC/W 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) 175
30
15
15
0
0
FIGURE 19. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HSTR = 10oC/W)
FIGURE 20. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HSTR = 25oC/W)
6
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Performance Curves
90 VDS , DRAIN TO SOURCE VOLTAGE (V)
(Continued)
MAX PULSE WIDTH = 100ms DC = 2% DC = 1% 8 TIME TO 175oC (s) 10
DUTY CYCLE = DC DC = 5%
DC = 10% 75 60 DC = 20%
TJ = 175oC ILIM = 0.210A RJC = 5.0oC/W
6
STARTING TJ = 75oC STARTING TJ = 100oC STARTING TJ = 125oC STARTING TJ = 150oC
45 30
4
DC = 50% 15 0
2
25
50
75 100 125 150 TA , AMBIENT TEMPERATURE (oC)
175
0
10
30 50 70 VDS , DRAIN TO SOURCE VOLTAGE (V)
90
FIGURE 21. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HSTR = 80oC/W)
10 STARTING TJ = STARTING TJ = 100oC STARTING TJ = 125oC STARTING TJ = 150oC 75oC
FIGURE 22. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 25oC/W) (HEATSINK THERMAL CAPACITANCE = 0.5J/oC)
10
8 TIME TO 175oC (s)
8 TIME TO 175oC (s) STARTING TJ = 75oC 6 STARTING TJ = 100oC STARTING TJ = 125oC 2 STARTING TJ = 150oC
6
4
4
2
0 10 30 50 70 VDS , DRAIN TO SOURCE VOLTAGE (V) 90
0
10
50 70 30 VDS , DRAIN TO SOURCE VOLTAGE (V)
90
FIGURE 23. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 10oC/W) (HEATSINK THERMAL CAPACITANCE = 1.0J/oC)
10 STARTING TJ = 75oC
FIGURE 24. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 5oC/W) (HEATSINK THERMAL CAPACITANCE = 2.0J/oC)
10
8 TIME TO 175oC (s) STARTING TJ = 100oC TIME TO 175oC (s)
8 STARTING TJ = 75oC 6 STARTING TJ = 100oC STARTING TJ = 125oC STARTING TJ = 150oC 4
6
4
STARTING TJ =
125oC
2 STARTING TJ = 0 10 150oC 90
2
30 50 70 VDS , DRAIN TO SOURCE VOLTAGE (V)
0
10
30 50 70 VDS , DRAIN TO SOURCE VOLTAGE (V)
90
FIGURE 25. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 2oC/W) (HEATSINK THERMAL CAPACITANCE = 4J/oC)
FIGURE 26. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 25oC/W) (HEATSINK THERMAL CAPACITANCE = 0.5J/oC)
7
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Performance Curves
10
(Continued)
10
8 TIME TO 175oC (s)
STARTING TJ = 75oC TIME TO 175oC (s) STARTING TJ = 100 C
o
8 STARTING TJ = 75oC 6 STARTING TJ = 100oC STARTING TJ = 125oC 2 STARTING TJ = 150oC 0
6
STARTING TJ = 125oC STARTING TJ = 150oC
4
4
2
0 10 30 50 70 90 VDS , DRAIN TO SOURCE VOLTAGE (V)
10
30
50
70
90
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 27. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 10oC/W) (HEATSINK THERMAL CAPACITANCE = 1.0J/oC)
10
FIGURE 28. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 5oC/W) (HEATSINK THERMAL CAPACITANCE = 2.0J/oC)
STARTING TJ = 75oC 8 TIME TO 175oC (s)
6 STARTING TJ = 100oC 4 STARTING TJ = 125oC 2 STARTING TJ = 150oC 0 10 30 50 70 90 VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 29. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 2oC/W) (HEATSINK THERMAL CAPACITANCE = 4J/oC)
8
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Temperature Compensated PSPICE Model for the RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
SUBCKT RLD03N06CLE 2 1 3; CA 12 8 0.547e-9 CB 15 14 0.547e-9 CIN 6 8 0.301e-9 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DESD1 91 9 DESD1MOD DESD2 91 7 DESD2MOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 20 17 18 66.5 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 2.96e-9 LSOURCE 3 7 2.96e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 QCONTROL 20 70 7 QMOD 1 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 1.123 RGATE 9 20 3200 RIN 6 8 1e9 RSOURCE1 8 70 RDSMOD 1.12 RSOURCE2 70 7 RSMOD 2.16 RVTO 18 19 RVTOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.22 .MODEL DBDMOD D (IS = 7.97e-17 RS = 1.82 TRS1 = 3.91e-3 TRS2 = 1.24e-5 CJO = 3.00e-10 TT = 1.83e-7) .MODEL DBKMOD D (RS = 3150 TRS1 =0 TRS2 = 0) .MODEL DESD1MOD D (BV = 13.54 TBV1 = 0 TBV2 = 0 RS = 45.5 TRS1 = 0 TRS2 = 0) .MODEL DESD2MOD D (BV = 11.46 TBV1 = -7.576e-4 TBV2 = -3.0e-6 RS = 0 TRS1 = 0 TRS2 = 0) .MODEL DPLCAPMOD D (CJO = 74.2e-12 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 1.67 KP = 3.40 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL QMOD NPN (BF =5) .MODEL RBKMOD RES (TC1 = 4e-4 TC2 = 1.13e-8) .MODEL RDSMOD RES (TC1 = 6.80e-3 TC2 = 6.5e-6) .MODEL RSMOD RES (TC1 = 2.95e-3 TC2 = -1e-6) .MODEL RVTOMOD RES (TC1 = -2.22e-3 TC2 = -1.95e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3 VOFF = -1) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1 VOFF = -3) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.85 VOFF = 2.15) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.15 VOFF = -2.85) .ENDS NOTE: 1. For further discussion of the PSPICE model consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records 1991. rev 4/18/94
5 DRAIN LDRAIN 2
DBREAK
10 11 +
DPLCAP
EBREAK
17 18 EVTO + 18 8
6 8 +
ESG 16 VTO +
RDRAIN
DBODY
GATE 1 LGATE DESD1 91 DESD2
RGATE 9
21 6 RIN CIN 8 MOS1
MOS2
RSOURCE1 RSOURCE2 70 7
LSOURCE 3 SOURCE
S1A 12 S1B CA EGS 13 8 13 + 6 8 14 13
S2A 15 S2B CB + EDS 5 8 14 IT RBREAK 17 18 RVTO 19 VBAT +
9
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE TO-220AB
3 LEAD JEDEC TO-220AB PLASTIC PACKAGE
A OP Q H1 D E1 45o D1 TERM. 4 E A1
INCHES SYMBOL A A1 b b1 c D D1 E E1 e e1 MIN 0.170 0.048 0.030 0.045 0.014 0.590 0.395 MAX 0.180 0.052 0.034 0.055 0.019 0.610 0.160 0.410 0.030 0.100 TYP 0.200 BSC 0.235 0.100 0.530 0.130 0.149 0.102 0.255 0.110 0.550 0.150 0.153 0.112
MILLIMETERS MIN 4.32 1.22 0.77 1.15 0.36 14.99 10.04 MAX 4.57 1.32 0.86 1.39 0.48 15.49 4.06 10.41 0.76 2.54 TYP 5.08 BSC 5.97 2.54 13.47 3.31 3.79 2.60 6.47 2.79 13.97 3.81 3.88 2.84 NOTES 3, 4 2, 3 2, 3, 4 5 5 6 2 -
L1
b1 b c
L 60o 1 2 3
e e1
J1
H1 J1 L
LEAD NO. 1 LEAD NO. 2 LEAD NO. 3 TERM. 4
- GATE - DRAIN - SOURCE - DRAIN
L1 OP Q
NOTES: 1. These dimensions are within allowable dimensions of Rev. J of JEDEC TO-220AB outline dated 3-24-87. 2. Lead dimension and finish uncontrolled in L1. 3. Lead dimension (without solder). 4. Add typically 0.002 inches (0.05mm) for solder coating. 5. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D. 6. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D. 7. Controlling dimension: Inch. 8. Revision 1 dated 1-93.
10
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE TO-251AA
3 LEAD JEDEC TO-251AA PLASTIC PACKAGE
E H1 A A1 TERM. 4 SEATING PLANE
INCHES SYMBOL A A1 b b1 b2 MIN 0.086 0.018 0.028 0.033 0.205 0.018 0.270 0.250 MAX 0.094 0.022 0.032 0.040 0.215 0.022 0.290 0.265
MILLIMETERS MIN 2.19 0.46 0.72 0.84 5.21 0.46 6.86 6.35 MAX 2.38 0.55 0.81 1.01 5.46 0.55 7.36 6.73 NOTES 3, 4 3, 4 3 3, 4 3, 4 5 5 6 2
b2
D
b1
L1 L
c D E
b
1 2 3
c
e e1
0.090 TYP 0.180 BSC 0.035 0.040 0.355 0.075 0.045 0.045 0.375 0.090
2.28 TYP 4.57 BSC 0.89 1.02 9.02 1.91 1.14 1.14 9.52 2.28
e e1
J1
H1 J1 L L1
LEAD NO. 1 LEAD NO. 2 LEAD NO. 3 TERM. 4
- GATE - DRAIN - SOURCE - DRAIN
NOTES: 1. These dimensions are within allowable dimensions of Rev. C of JEDEC TO-251AA outline dated 9-88. 2. Solder finish uncontrolled in this area. 3. Dimension (without solder). 4. Add typically 0.002 inches (0.05mm) for solder plating. 5. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D. 6. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D. 7. Controlling dimension: Inch. 8. Revision 2 dated 10-95.
11
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE TO-252AA
SURFACE MOUNT JEDEC TO-252AA PLASTIC PACKAGE
E H1 A A1 SEATING PLANE D L2 1 3 L
INCHES SYMBOL A A1 b b1 b2 b3 c D E e e1 H1 J1 L
0.265 (6.7)
MILLIMETERS MIN 2.19 0.46 0.72 0.84 5.21 4.83 0.46 6.86 6.35 MAX 2.38 0.55 0.81 1.01 5.46 0.55 7.36 6.73 NOTES 4, 5 4, 5 4 4, 5 2 4, 5 7 7 4, 6 3 2
b2
MIN 0.086 0.018 0.028 0.033 0.205 0.190 0.018 0.270 0.250
MAX 0.094 0.022 0.032 0.040 0.215 0.022 0.290 0.265
b e e1
TERM. 4
b1
L1
c
J1 0.265 (6.7)
0.090 TYP 0.180 BSC 0.035 0.040 0.100 0.020 0.025 0.170 0.045 0.045 0.115 0.040 -
2.28 TYP 4.57 BSC 0.89 1.02 2.54 0.51 0.64 4.32 1.14 1.14 2.92 1.01 -
b3
L3
L1 L2 L3
0.070 (1.8) 0.118 (3.0) BACK VIEW 0.063 (1.6) 0.090 (2.3) 0.090 (2.3) MINIMUM PAD SIZE RECOMMENDED FOR SURFACE-MOUNTED APPLICATIONS 0.063 (1.6)
LEAD NO. 1 LEAD NO. 3 TERM. 4
- GATE - SOURCE - DRAIN
NOTES: 1. These dimensions are within allowable dimensions of Rev. B of JEDEC TO-252AA outline dated 9-88. 2. L3 and b3 dimensions establish a minimum mounting surface for terminal 4. 3. Solder finish uncontrolled in this area. 4. Dimension (without solder). 5. Add typically 0.002 inches (0.05mm) for solder plating. 6. L1 is the terminal length for soldering. 7. Position of lead to be measured 0.090 inches (2.28mm) from bottom of dimension D. 8. Controlling dimension: Inch. 9. Revision 5 dated 10-95.
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RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE TO-252AA
16mm TAPE AND REEL
22.4mm 1.5mm DIA. HOLE 4.0mm 2.0mm 1.75mm C L 16mm 330mm 50mm 8.0mm
13mm
16.4mm
USER DIRECTION OF FEED
COVER TAPE
GENERAL INFORMATION 1. USE "9A" SUFFIX ON PART NUMBER. 2. 2500 PIECES PER REEL. 3. ORDER IN MULTIPLES OF FULL REELS ONLY. 4. MEETS EIA-481 REVISION "A" SPECIFICATIONS.
Revision 5 dated 10-95
Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries.
Sales Office Headquarters
For general information regarding Harris Semiconductor and its products, call 1-800-4-HARRIS UNITED STATES Harris Semiconductor P. O. Box 883, Mail Stop 53-210 Melbourne, FL 32902 TEL: 1-800-442-7747 (407) 729-4984 FAX: (407) 729-5321 EUROPE Harris Semiconductor Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2-724-2111 SOUTH ASIA Harris Semiconductor H.K. Ltd. 13/F Fourseas Building 208-212 Nathan Road Tsimshatsui, Kowloon Hong Kong TEL: (852) 723-6339 NORTH ASIA Harris K.K. Kojimachi-Nakata Bldg. 4F 5-3-5 Kojimachi Chiyoda-ku, Tokyo 102 Japan TEL: (81) 3-3265-7571 TEL: (81) 3-3265-7572 (Sales)
SEMICONDUCTOR
13

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